TY  - BOOK
AU  - Narendra,Siva G.
AU  - Chandrakasan,Anantha P.
TI  - Leakage in nanometer CMOS technologies
SN  - 0387257373
AV  - TK7871.99.M44 L43 2006
U1  - 621.38412 
PY  - 2006///
CY  - New York
PB  - Springer
KW  - Metal oxide semiconductors, Complementary
KW  - Design and construction
KW  - Integrated circuits
KW  - Electric leakage
KW  - Prevention
N1  - Includes bibliographical references and index; TOC; Taxonomy of leakage : sources, impact, and solutions --
Leakage dependence on input vector / Siva Narendra ... [et al.] --
Power gating and dynamic voltage scaling / Benton Calhoun, James Kao, and Anantha Chandrakasan --
Methodologies for power gating / Kimiyoshi Usami and Takayasu Sakurai --
Body biasing / Tadahiro Kuroda and Takayasu Sakurai --
Process variation and adaptive design / Siva Narendra ... [et al.] --
Memory leakage reduction / Takayuki Kawahara and Kiyoo Itoh --
Active leakage reduction and multi-performance devices / Siva Narendra ... [et al.] --
Impact of leakage power and variation on testing / Ali Keshavarzi and Kaushik Roy --
Case study : leakage reduction in Hitachi/Renesas microprocessors / Masayuki Miyazaki, Hiroyuki Mizuno, and Takayuki Kawahara --
Case study : leakage reduction in the Intel Xscale microprocessor / Lawrence Clark --
Transistor design to reduce leakage / Sagar Suthram, Siva Narendra, and Scott Thompson; EEE
N2  - Summary:
Covers promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from the first principles. This title highlights different device design choices that exist to mitigate increases in the leakage components as technology scales
UR  - http://www.loc.gov/catdir/toc/fy0607/2005932184.html
UR  - http://www.loc.gov/catdir/enhancements/fy0663/2005932184-d.html
UR  - http://www.worldcat.org/title/leakage-in-nanometer-cmos-technologies/oclc/62510295&referer=brief_results
UR  - http://lib.ewubd.edu/ebook/5989
ER  -