TY  - BOOK
AU  - Patmaṉāpaṉ,ṬiĀr
AU  - Tripura Sundari,B.Bala
TI  - Design through Verilog HDL
SN  - 0471441481 (cloth)
AV  - TK7885.7 .P37 2004
U1  - 621.392 
PY  - 2004///
CY  - Piscataway, NJ, Hoboken, NJ, Noida
PB  - IEEE Press, Wiley-Interscience
KW  - Verilog (Computer hardware description language)
N1  - Includes bibliographical references (p. 449-450) and index; TOC; Machine generated contents note: 1. Introduction to VLSI Design --
2. Introduction to Verilog --
3. Language Constructs and Conventions in Verilog --
4. Gate Level Modeling --
1 --
5. Gate Level Modeling --
2 --
6. Modeling at Data Flow Level --
7. Behavioral Modeling --
1 --
8. Behavioral Modeling II --
9. Functions, Tasks, and User-Defined Primitives --
10. Switch Level Modeling --
11. System Tasks, Functions, and Compiler Directives --
12. Queues, Plas, and FSMS --
App. A Keywords and Their Significance --
App. B Truth Tables of Gates an Switches; ETE
UR  - http://www.worldcat.org/title/design-through-verilog-hdl/oclc/85820224&referer=brief_results
UR  - http://lib.ewubd.edu/ebook/4729
ER  -