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Computer architecture : a quantitative approach / John L. Hennessy and David A. Patterson.

By: Hennessy, John LContributor(s): Patterson, David AMaterial type: TextTextLanguage: English Publication details: Massachusetts : Morgan Kaufmann Publishers, 2019. Edition: 6th edDescription: Various paginitation : ill. ; 24 cmISBN: 9780128119051Subject(s): Computer architecture | Computers and ITDDC classification: 004.22 Online resources: Worldcat details
Contents:
Table of contents Fundamentals of quantitative design and analysis Memory hierarchy design Instruction-level parallelism and its exploitation Data-level parallelism in vector, SIMD, and GPU architectures Thread-level parallelism Warehouse-scale computers to exploit request-level and data-level parallelism Domain-specific architectures Appendix A. Instruction set principles ; Appendix B. Review of memory hierarchy ; Appendix C. Pipelining : basic and intermediate concepts Online appendices. Appendix D. Storage systems ; Appendix E. Embedded systems ; Appendix F. Interconnection networks ; Appendix G. Vector processors in more depth ; Appendix H. Hardware and software for VLIW and EPIC ; Appendix I. Large-scale multiprocessors and scientific applications ; Appendix J. Computer arithmetic ; Appendix K. Survey of instruction set architectures ; Appendix L. Advanced concepts on address translation ; Appendix M. Historical perspectives and references
Summary: Computer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students and practitioners of computer design for over 20 years. The sixth edition of this classic textbook is fully revised with the latest developments in processor and system architecture. It now features examples from the RISC-V (RISC Five) instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC. True to its original mission of demystifying computer architecture, this edition continues the longstanding tradition of focusing on areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design.
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Holdings
Item type Current library Collection Call number Copy number Status Date due Barcode Item holds
Text Text Dr. S. R. Lasker Library, EWU
Reserve Section
Non-fiction 004.22 HEC 2019 (Browse shelf(Opens below)) C-1 Not For Loan 31589
Text Text Dr. S. R. Lasker Library, EWU
Circulation Section
Non-fiction 004.22 HEC 2019 (Browse shelf(Opens below)) C-2 Available 31590
Total holds: 0

Includes bibliographical references and index.

Table of contents Fundamentals of quantitative design and analysis
Memory hierarchy design
Instruction-level parallelism and its exploitation
Data-level parallelism in vector, SIMD, and GPU architectures
Thread-level parallelism
Warehouse-scale computers to exploit request-level and data-level parallelism
Domain-specific architectures
Appendix A. Instruction set principles ; Appendix B. Review of memory hierarchy ; Appendix C. Pipelining : basic and intermediate concepts
Online appendices. Appendix D. Storage systems ; Appendix E. Embedded systems ; Appendix F. Interconnection networks ; Appendix G. Vector processors in more depth ; Appendix H. Hardware and software for VLIW and EPIC ; Appendix I. Large-scale multiprocessors and scientific applications ; Appendix J. Computer arithmetic ; Appendix K. Survey of instruction set architectures ; Appendix L. Advanced concepts on address translation ; Appendix M. Historical perspectives and references

Computer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students and practitioners of computer design for over 20 years. The sixth edition of this classic textbook is fully revised with the latest developments in processor and system architecture. It now features examples from the RISC-V (RISC Five) instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC. True to its original mission of demystifying computer architecture, this edition continues the longstanding tradition of focusing on areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design.

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