MARC details
| 000 -LEADER |
|---|
| fixed length control field |
01820cam a2200361 a 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
3989 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
BD-DhEWU |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20180227204826.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
940414s1994 nyua 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
0070163332 |
|
|---|
| International Standard Book Number |
0071132716 (Cover) |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCLC) 29428443 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
BD-DhEWU |
| Language of cataloging |
eng |
| Transcribing agency |
BD-DhEWU |
| 041 ## - LANGUAGE CODE |
|---|
| Language code of text/sound track or separate title |
eng |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Edition number |
22 |
| Classification number |
621.3950285 |
| Item number |
MIS 1994 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
De Micheli, Giovanni |
| 9 (RLIN) |
10072 |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Synthesis and optimization of digital circuits / |
| Statement of responsibility, etc |
Giovanni De Micheli |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
New York ; |
| -- |
London : |
| -- |
New Dehi : |
| Name of publisher, distributor, etc |
McGraw-Hill, |
| Date of publication, distribution, etc |
c1994 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xviii, 579 p ; |
| Dimensions |
23 cm |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
McGraw-Hill series in electrical and computer engineering. Electronics and VLSI circuits |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Chapter 1: Introduction --<br/>Chapter 2: Background --<br/>Chapter 3: Hardware modeling --<br/>Chapter 4: Architectural synthesis --<br/>Chapter 5: Scheduling algorithms --<br/>Chapter 6: Resource sharing and binding --<br/>Chapter 7: Two-level combinational logic optimization --<br/>Chapter 8: Multiple-level combinational logic optimization --<br/>Chapter 9: Sequential logic optimization --<br/>Chapter 10: Cell-library binding --<br/>Chapter 11: State-of-the-art and future trends. |
| Title |
TOC |
| 526 ## - STUDY PROGRAM INFORMATION NOTE |
|---|
| Program name |
EEE |
| 590 ## - LOCAL NOTE (RLIN) |
|---|
| Local note |
Shaharima Parvin |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Digital integrated circuits |
| General subdivision |
Design and construction |
| -- |
Data processing |
| 9 (RLIN) |
10073 |
|
|---|
| Topical term or geographic name as entry element |
Digital electronics |
| General subdivision |
Data processing |
| 9 (RLIN) |
10074 |
|
|---|
| Topical term or geographic name as entry element |
Computer-aided design |
| 9 (RLIN) |
10075 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
McGraw-Hill series in electrical and computer engineering. |
| 9 (RLIN) |
22218 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
WorldCat details |
| Uniform Resource Identifier |
https://www.worldcat.org/title/synthesis-and-optimization-of-digital-circuits/oclc/29428443&referer=brief_results |
|
|---|
| Materials specified |
E-book Fulltext |
| Uniform Resource Identifier |
http://lib.ewubd.edu/ebook/3989 |
| 942 42 - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Text |
| Koha issues (borrowed), all copies |
2 |